Recently, semiconductor dice have been supplied by manufacturers in an unpackaged or bare configuration. Chip scale packages have also been developed with an outline that is substantially equivalent to a bare die. As with conventionally packaged dice, chip scale packages and bare dice must be tested following manufacture to certify quality and reliability. The dice can be evaluated for speed and functionality. In addition, burn-in testing can be conducted at elevated temperatures. These testing requirements have led to the development of test carriers that hold a single die for burn-in and other tests. Exemplary test carriers are disclosed in U.S. Pat. Nos. 5,302,891; 5,408,190; 5,495,179 and 5,519,332 to Wood et al.
This type of test carrier includes external leads adapted to electrically connect to test circuitry via a burn-in board or other electrical receptacle. In addition, an interconnect component of the test carrier provides a temporary electrical connection between the bond pads on the die and external leads on the carrier. In the assembled carrier, a force distribution mechanism biases the device under test (DUT) against the interconnect.
In order to accommodate volume semiconductor manufacture and the large number of different types of dice, these carriers need to be inexpensive to manufacture. In addition, in order to provide reliable testing for the dice, the electrical characteristics of the carriers must be within acceptable values. Important electrical characteristics for carriers include the inductance, resistance and capacitance of the conductive paths through the carrier to the DUT.
Typically the carriers include conductors in electrical communication with the external leads for the carriers. These conductors can be formed of a highly conductive metal deposited on a surface of the carrier base or formed internally within the carrier base. The interconnect also includes conductors in electrical communication with contact members that electrically connect with the bond pads on the die.
The electrical path between the conductors on the carrier and the conductors on the interconnect can be a wire bond or a mechanical electrical connection such as clips. It is desirable to minimize the length of this electrical path in order reduce parasitic induction and cross coupling of the test signals applied to the die. In addition, it is desirable that this electrical path be low resistance and reliable even with long term handling of the carrier in a production environment. For example, with an electrical path formed by wire bonding, the placement and integrity of the bond sites during their formation and continued usage can be a factor in the electrical performance of the carrier.
The present invention is directed to a carrier that does not include external leads and conductors on the carrier base. Rather the carrier includes an interconnect formed on the carrier base and adapted for direct electrical connection to external test circuitry. In addition, the present invention is directed to an improved method for fabricating a carrier with a direct connect interconnect.